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1. general description the uja1075a core system basis chip (sbc) replaces the basic discrete components commonly found in electronic control unit s (ecu) with a high-speed controller area network (can) and a local interconnect network (lin) interface. the uja1075a supports the networking applications used to control power and sensor peripherals by using a high-speed can as the main network interface and the lin interface as a local sub-bus. the core sbc contains the following integrated devices: ? high-speed can transceiver, inter-operable and downward compatible with can transceiver tja1042, and compatible with the iso 11898-2 and iso 11898-5 standards ? lin transceiver complia nt with lin 2.1, li n 2.0 and sae j2602, and compatible with lin 1.3 ? advanced independent watchdog (uja1075a/xx/wd versions) ? 250 ma voltage regulator for supplying a mi crocontroller; extendable with external pnp transistor for increase d current capability and dissipation distribution ? separate voltage regulator for supplying the on-board can transceiver ? serial peripheral interface (spi) (full duplex) ? 2 local wake-up input ports ? limp home output port in addition to the advantages gained from integrating these common ecu functions in a single package, the core sbc offers an intelligent combination of system-specific functions such as: ? advanced low-power concept ? safe and controlled system start-up behavior ? detailed status reporting on system and sub-system levels the uja1075a is designed to be used in combination with a microcontroller that incorporates a can controller. the sbc ensure s that the microcontroller always starts up in a controlled manner. uja1075a high-speed can/lin core system basis chip rev. 01 ? 9 july 2010 product data sheet
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 2 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 2. features and benefits 2.1 general ? contains a full set of can and lin ecu functions: ? can transceiver and lin transceiver ? scalable 3.3 v or 5 v voltage regulator delivering up to 250 ma for a microcontroller and peripheral circuitry; an external pnp transistor can be connected for better heat distribution over the pcb ? separate voltage regulator fo r the can transceiver (5 v) ? watchdog with window and timeout modes and on-chip oscillator ? serial peripheral interface (spi) for communicating with the microcontroller ? ecu power management system ? designed for automotive applications: ? enhanced electromagnetic co mpatibility (emc) performance ? 8 kv electrostatic discharge (esd) protection human body model (hbm) on the can/lin bus pins and the wake-up pins ? 6 kv electrostatic discharge protection iec 61000-4-2 on the can/lin bus pins and the wake-up pins ? 58 v short-circuit proof can/lin bus pins ? battery and can/lin bus pins are protect ed against transients in accordance with iso 7637-3 ? supports remote flash programming via the can bus ? small 6.1 mm 11 mm htssop32 package with low thermal resistance ? pb-free; restriction of hazardous subst ances directive (rohs) and dark green compliant 2.2 can transceiver ? iso 11898-2 and iso 11898-5 compliant high-speed can transceiver ? dedicated low dropout voltage regulator for the can bus: ? independent of the microcontroller supply ? significantly improves emc performance ? bus connections are truly floating when power is off ? split output pin for stabilizing the recessive bus level 2.3 lin transceiver ? lin 2.1 compliant lin transceiver ? compliant with sae j2602 ? downward compatible with lin 2.0 and lin 1.3 ? low slope mode for optimized emc performance ? integrated lin termination diode at pin dlin 2.4 power management ? wake-up via can, lin or local wake-up pins with wake-up source detection ? 2 wake-up pins:
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 3 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip ? wake1 and wake2 inputs can be swit ched off to reduce current flow ? output signal (wbias) to bias the wake-up pins, selectable sampling time of 16 ms or 64 ms ? standby mode with very low standby current a nd full wake-up capability; v1 active to maintain supply to the microcontroller ? sleep mode with very low sleep cu rrent and full wake-up capability 2.5 control and diagnostic features ? safe and predictable behavior under all conditions ? programmable watchdog with independent clock source: ? window, timeout (with optional cyclic wake-up) and off modes supported (with automatic re-enable in the event of an interrupt) ? 16-bit serial peripheral interface (spi) for configuration, control and diagnosis ? global enable output for cont rolling safety-critical hardware ? limp home output (limp) fo r activating application-spec ific ?limp home? hardware in the event of a serious system malfunction ? overtemperature shutdown ? interrupt output pin; interrupts can be individually configured to signal v1/v2 undervoltage, can/lin/local wake-up and cyclic and power-on interrupt events ? bidirectional reset pin with variable power- on reset length to support a variety of microcontrollers ? software-initiated system reset 2.6 voltage regulators ? main voltage regulator v1: ? scalable voltage regulator for the microcontroller, its peripherals and additional external transceivers ? 2 % accuracy ? 3.3 v and 5 v versions available ? delivers up to 250 ma and can be combined with an external pnp transistor for better heat distribution over the pcb ? selectable current threshold at which the ex ternal pnp transistor starts to deliver current ? undervoltage warning at 90 % of nominal output voltage and undervoltage reset at 90 % or 70 % of nominal output voltage ? can operate at v bat voltages down to 4.5 v (e.g. during cranking), in accordance with iso 7637 pulse 4/4b and iso 16750-2 ? stable output under all conditions ? voltage regulator v2 for can transceiver: ? dedicated voltage regulator for on-chip high-speed can transceiver ? undervoltage warning at 90 % of nominal output voltage ? can be switched off; can transceiver can be supplied by v1 or by an external voltage regulator ? can operate at v bat voltages down to 5.5 v (e.g. during cranking) in accordance with iso 7637, pulse 4 ? stable output under all conditions
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 4 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 3. ordering information [1] uja1075atw/5v0xx versions contain a 5 v regulator (v1); uja1075a tw/3v3xx versions contain a 3. 3 v regulator (v1); wd versions contain a watchdog. 4. block diagram table 1. ordering information type number [1] package name description version uja1075atw/5v0/wd htssop32 plastic thermal enh anced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad sot549-1 uja1075atw/3v3/wd uja1075atw/5v0 uja1075atw/3v3 fig 1. block diagram system controller lin bat v1 uv uja1075a sdi hs-can sck scsn sdo wake2 wake1 en wdoff lin rxdl txdl dlin bat bat limp split rxdc txdc canl canh v2 osc temp intn rstn ext. pnp ctrl vexcc vexctrl v2 uv v2 v1 v1 v2 gnd wake wbias 015aaa179
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 5 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 5. pinning information 5.1 pinning 5.2 pin description fig 2. pin configuration uja1075a i.c. bat i.c. vexctrl txdl test2 v1 vexcc rxdl wbias rstn i.c. intn dlin en lin sdi split sdo gnd sck canl scsn canh txdc v2 rxdc wake2 test1 wake1 wdoff limp 015aaa180 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 table 2. pin description symbol pin description i.c. 1 internally connected; should be left floating i.c. 2 internally connected; should be left floating txdl 3 lin transmit data input v1 4 voltage regulator output for the microcontroller (5 v or 3.3 v depending on sbc version) rxdl 5 lin receive data output rstn 6 reset input/output to and from the microcontroller intn 7 interrupt output to the microcontroller en 8 enable output sdi 9 spi data input sdo 10 spi data output sck 11 spi clock input scsn 12 spi chip select input txdc 13 can transmit data input rxdc 14 can receive data output test1 15 test pin; pin should be connected to ground wdoff 16 wdoff pin for deactivating the watchdog limp 17 limp home output
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 6 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip the exposed die pad at the bottom of the package allows for better heat dissipation from the sbc via the printed-circuit board. the exposed die pad is not connected to any active part of the ic and can be left floating, or can be connected to gnd. 6. functional description the uja1075a combines the functionality of a high-speed can transceiver, a lin transceiver, two voltage regulators and a watchdog (uja1075a/xx/wd versions) in a single, dedicated chip. it handles the power- up and power-down functionality of the ecu and ensures advanced system reliability. the sbc offers wake-up by bus activity, by cyclic wake-up and by the activation of exte rnal switches. additionally, it provides a periodic control signal for pulsed testing of wake-up switches, allowing low-current operation even when the wake-up s witches are closed in standby mode. all transceivers are optimized to be highly flexible with regard to bus topologies. in particular, the high-speed can transceiver is opt imized to reduce ringing (bus reflections). v1, the main voltage regulator, is designed to power the ecu's microcontroller, its peripherals and additional external transceivers. an external pnp transistor can be added to improve heat distribution. v2 supplies th e integrated high-speed can transceiver. the watchdog is clocked directly by the on-chip oscillator and can be operated in window, timeout and off modes. wake1 18 local wake-up input 1 wake2 19 local wake-up input 2 v2 20 5 v voltage regulator output for can canh 21 canh bus line canl 22 canl bus line gnd 23 ground split 24 can bus common mode stabilization output lin 25 lin bus line dlin 26 lin termination resistor connection i.c. 27 internally connected; should be left floating wbias 28 control pin for external wake biasing transistor vexcc 29 current measurement for external pnp transistor; this pin is connected to the collector of the external pnp transistor test2 30 test pin; pin should be connected to ground vexctrl 31 control pin of the ex ternal pnp transistor; this pin is connected to the base of the external pnp transistor bat 32 battery supply for the sbc table 2. pin description ?continued symbol pin description
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 7 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.1 system controller 6.1.1 introduction the system controller manages register confi guration and controls the internal functions of the sbc. detailed device status inform ation is collected and presented to the microcontroller. the system controller also provides the reset and interrupt signals. the system controller is a state machine. th e sbc operating modes, and how transitions between modes are trigger ed, are illustrated in figure 3 . these modes are discussed in more detail in the following sections.
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 8 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip fig 3. uja1075a system controller v1: on v2: off can/lin: lowpower/off watchdog: timeout/off mc = 00 standby watchdog trigger v1: on v2: on/off can/lin: active/lowpower watchdog: window/ timeout/off mc = 1x normal v1: off v2: off can/lin: lowpower/off watchdog: off rstn: low mc = 01 sleep successful watchdog trigger watchdog overflow or v1 undervoltage v1: off v2: off can/lin: off and high resistance watchdog: off intn: high off v bat below power-on threshold v th(det)pon v bat below power-off threshold v th(det)poff (from all modes) v1: off v2: off limp home = low (active) can/lin: off and high resistance watchdog: off overtemp from standby or normal chip temperature above otp activation threshold t th(act)otp chip temperature below otp release threshold t th(rel)otp v bat above power-on threshold v th(det)pon mc = 01 and intn = high and one wake-up enabled and no wake-up pending wake-up event if enabled mc = 01 and intn = high and one wake-up enabled and no wake-up pending reset event or mc = 00 mc = 10 or mc = 11 015aaa07 3
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 9 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.1.2 off mode the sbc switches to off mode from all other modes if the battery supply drops below the power-off detection threshold (v th(det)poff ). in off mode, the voltage regulators are disabled and the bus systems are in a high-resistive st ate. the can bus pins are floating in this mode. as soon as the battery supply rises above the power-on detection threshold (v th(det)pon ), the sbc goes to standby mode, and a system reset is executed (reset pulse width of t w(rst) , long or short; see section 6.5.1 and table 11 ). 6.1.3 standby mode the sbc will enter standby mode: ? from off mode if v bat rises above the power-on detection threshold (v th(det)pon ) ? from sleep mode on the occurrence of a can, lin or local wake-up event ? from overtemp mode if the chip temperature drops below the overtemperature protection release threshold, t th(rel)otp ? from normal mode if bit mc is set to 00 or a system reset is performed (see section 6.5 ) in standby mode, v1 is switched on. the ca n and lin transceivers will either be in a low-power state (lowpower mode; stbcc/stbcl = 1; see table 6 ) with bus wake-up detection enabled or completely switched off (off mode; stbcc/stbcl = 0) - see section 6.7.1 and section 6.8.1 . the watchdog can be running in timeout mode or off mode, depending on the state of the wdoff pin and the setting of the watchdog mode control bit (wmc) in the wd_and_status register ( ta b l e 4 ). the sbc will exit standby mode if: ? normal mode is selected by setting bits mc to 10 (v2 disabled) or 11 (v2 enabled) ? sleep mode is selected by setting bits mc to 01 ? the chip temperature rises above the over temperature protection (otp) activation threshold, t th(act)otp , causing the sbc to enter over temp mode 6.1.4 normal mode normal mode is selected from standby mode by setting bits mc in the mode_control register ( table 5 ) to 10 (v2 disabled) or 11 (v2 enabled). in normal mode, the can physical layer w ill be enabled (active mode; stbcc = 0; see ta b l e 6 ) or in a low-power state (lowpower mode; stbcc = 1) with bus wake-up detection active. in normal mode, the lin physical layer will be enabled (active mode; stbcl = 0; see ta b l e 6 ) or in a low-power state (lowpower mode; stbcl = 1) with bus wake-up detection active. the sbc will exit normal mode if: ? standby mode is selected by setting bits mc to 00 ? sleep mode is selected by setting bits mc to 01 ? a system reset is generated (see section 6.1.3 ; the sbc will enter standby mode)
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 10 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip ? the chip temperature rises above the otp activation threshold, t th(act)otp , causing the sbc to switch to overtemp mode 6.1.5 sleep mode sleep mode is selected from standby mode or normal mode by setting bits mc in the mode_control register ( ta b l e 5 ) to 01. the sbc will enter slee p mode providing there are no pending interrupts (pin intn = high) or wake-up events and at least one wake-up source is enabled (can, lin or wake). any attempt to enter sleep mode while one of these conditions has no t been satisfied will result in a short reset (3.6 ms minimum pulse width; see section 6.5.1 and ta b l e 11 ). in sleep mode, v1 and v2 are off and the bu s transceivers will be switched off (off mode; stbcc/stbcl = 0; see ta b l e 6 ) or in a low-power state (lowpower mode; stbcc/stbcl = 1) with bus wake-up detection active - see section 6.7.1 and section 6.8.1 ). the watchdog is off and the reset pin is low. a can, lin or local wake-up event will cause the sbc to switch fr om sleep mode to standby mode, generating a (short or long; see section 6.5.1 ) system reset. the value of the mode control bits (mc) will be changed to 00 and v1 will be enabled. 6.1.6 overtemp mode the sbc will enter overtemp mode from norma l mode or standby mode when the chip temperature exceeds the overtemperatur e protection activation threshold, t th(act)otp , in overtemp mode, the volta ge regulators are switched of f and the bus systems are in a high-resistive state. when the sbc enters overtemp mode, the rstn pin is driven low and the limp home control bit, lhc, is se t so that the limp pin is driven low. the chip temperature must drop a hysteresis level below the overtemperature shutdown threshold before the sbc can exit overtemp mode. after leaving overtemp mode the sbc enters standby mode and a system rese t is generated (reset pulse width of t w(rst) , long or short; see section 6.5.1 and table 11 ). 6.2 spi 6.2.1 introduction the serial peripheral interface (spi) provides the communication link with the microcontroller, supporting multi-slave operat ions. the spi is configured for full duplex data transfer, so status information is returned when new control data is shifted in. the interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. the spi uses four interface signals for synchronization and data transfer: ? scsn: spi chip select; active low ? sck: spi clock; default level is low due to low-power concept ? sdi: spi data input ? sdo: spi data output; floating when pin scsn is high bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge (see figure 4 ).
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 11 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.2.2 register map the first three bits (a2, a1 and a0) of the message header define the register address. the fourth bit (ro) defines the selected register as read/write or read only. fig 4. spi timing protocol scsn sck 01 sampled floating floating 015aaa20 5 x x msb 14 13 12 01 lsb msb 14 13 12 01 lsb x sdi sdo 02 03 04 15 16 table 3. register map address bits 15, 14 and 13 write access bit 12 = 0 read/write access bits 11... 0 000 0 = read/write, 1 = read only wd_and_status register 001 0 = read/write, 1 = read only mode_control register 010 0 = read/write, 1 = read only int_control register 011 0 = read/write, 1 = read only int_status register
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 12 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.2.3 wd_and_status register [1] bit nwp is set to its default value (100) after a reset. table 4. wd_and_status register bit symbol access power-on default description 15:13 a2, a1, a0 r 000 register address 12 ro r/w 0 access status 0: register set to read/write 1: register set to read only 11 wmc r/w 0 watchdog mode control 0: normal mode: watchdog in window mode; standby mode: watchdog in timeout mode 1: normal mode: watchdog in timeout mode; standby mode: watchdog in off mode 10:8 nwp [1] r/w 100 nominal watchdog period 000: 8 ms 001: 16 ms 010: 32 ms 011: 64 ms 100: 128 ms 101: 256 ms 110: 1024 ms 111: 4096 ms 7 wos/swr r/w - watchdog off status/software reset 0: wdoff pin low; watchdog mode determined by bit wmc 1: watchdog disabled due to high level on pin wdoff; results in software reset 6 v1s r - v1 status 0: v1 output voltage above 90 % undervoltage recovery threshold (v uvr ;see ta b l e 1 0 ) 1: v1 output voltage below 90 % undervoltage detection threshold (v uvd ;see ta b l e 1 0 ) 5 v2s r - v2 status 0: v2 output voltage above undervoltage release threshold (v uvr ;see ta b l e 1 0 ) 1: v2 output voltage below undervoltage detection threshold (v uvd ;see ta b l e 1 0 ) 4 wls1 r - wake-up 1 status 0: wake1 input voltage below switching threshold (v th(sw) ) 1: wake1 input voltage above switching threshold (v th(sw) ) 3 wls2 r - wake-up 2 status 0: wake2 input voltage below switching threshold (v th(sw) ) 1: wake2 input voltage above switching threshold (v th(sw) ) 2:0 reserved r 000
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 13 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.2.4 mode_control register [1] bit lhwc is set to 1 after a reset. [2] bit lhc is set to 1 after a reset, if lhwc was set to 1 prior to the reset. table 5. mode_control register bit symbol access power-on default description 15:13 a2, a1, a0 r 001 register address 12 ro r/w 0 access status 0: register set to read/write 1: register set to read only 11:10 mc r/w 00 mode control 00: standby mode 01: sleep mode 10: normal mode; v2 off 11: normal mode; v2 on 9lhwc [1] r/w 1 limp home warning control 0: no limp home warning 1: limp home warning is set; next reset will activate limp output 8lhc [2] r/w 0 limp home control 0: limp pin set floating 1: limp pin driven low 7 enc r/w 0 enable control 0: en pin driven low 1: en pin driven high in normal mode 6 lsc r/w 0 lin slope control 0: normal slope, 20 kbit/s 1: low slope, 10.4 kbit/s 5 wbc r/w 0 wake bias control 0: pin wbias floating if wsen = 0; 16 ms sampling if wsen = 1 1: pin wbias low if wsen = 0; 64 ms sampling if wsen = 1 4 pdc r/w 0 power distribution control 0: v1 threshold current for activating the external pnp transistor; load current rising; i th(act)pnp = 85 ma; v1 threshold current for deactivating the external pnp transistor; load current falling; i th(deact)pnp =50ma; see figure 7 1: v1 threshold current for activating the external pnp transistor; load current rising; i th(act)pnp = 50 ma; v1 threshold current for deactivating the external pnp transistor; load current falling; i th(deact)pnp =15ma; see figure 7 3:0 reserved r 0000
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 14 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.2.5 int_control register table 6. int_control register bit symbol access power-on default description 15:13 a2, a1, a0 r 010 register address 12 ro r/w 0 access status 0: register set to read/write 1: register set to read only 11 v1uie r/w 0 v1 undervoltage interrupt enable 0: v1 undervoltage warning interrupts cannot be requested 1: v1 undervoltage warning interrupts can be requested 10 v2uie r/w 0 v2 undervoltage interrupt enable 0: v2 undervoltage warning interrupts cannot be requested 1: v2 undervoltage warning interrupts can be requested 9 stbcl r/w 0 lin standby control 0: when the sbc is in normal mode (mc = 1x): lin is in active mode. the wake-up flag (visible on rxdl) is cleared regardless of the value of v bat . when the sbc is in standby/sleep mode (mc = 0x): lin is in off mode. bus wake-up de tection is disabled. lin wake-up interrupts cannot be requested. 1: lin is in lowpower mode with bus wake-up detection enabled, regardless of the sbc mode (mc = xx). lin wake-up interrupts can be requested. 8 reserved r 0 7:6 wic1 r/w 00 wake-up interrupt 1 control 00: wake-up interrupt 1 disabled 01: wake-up interrupt 1 on rising edge 10: wake-up interrupt 1 on falling edge 11: wake-up interrupt 1 on both edges 5:4 wic2 r/w 00 wake-up interrupt 2 control 00: wake-up interrupt 2 disabled 01: wake-up interrupt 2 on rising edge 10: wake-up interrupt 2 on falling edge 11: wake-up interrupt 2 on both edges 3 stbcc r/w 0 can standby control 0: when the sbc is in normal mode (mc = 1x): can is in active mode. the wake-up flag (visible on rxdc) is cleared regardless of v2 output voltage. when the sbc is in standby/sleep mode (mc = 0x): can is in off mode. bus wake-up detection is disabled. can wake-up interrupts cannot be requested. 1: can is in lowpower mode with bus wake-up detection enabled, regardless of the sbc mode (mc = xx). can wake-up interrupts can be requested.
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 15 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 2 rthc r/w 0 reset threshold control 0: the reset threshold is set to the 90 % v1 undervoltage detection voltage (v uvd ; see table 10 ) 1: the reset threshold is set to the 70 % v1 undervoltage detection voltage (v uvd ; see table 10 ) 1 wse1 r/w 0 wake1 sample enable 0: sampling continuously 1: sampling of wake1 is synchroniz ed with wbias (sampl e rate controlled by wbc) 0 wse2 r/w 0 wake2 sample enable 0: sampling continuously 1: sampling of wake1 is synchroniz ed with wbias (sampl e rate controlled by wbc) table 6. int_control register ?continued bit symbol access power-on default description
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 16 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.2.6 int_status register [1] an interrupt can be cleared by writing 1 to the relevant bit in the int_status register. 6.3 on-chip oscillator the on-chip oscillator provides the timing reference for t he on-chip watc hdog and the internal timers. the on-chip oscillator is supplied by an internal supply that is connected to v bat and is independent of v1/v2. table 7. int_status register [1] bit symbol access power-on default description 15:13 a2, a1, a0 r 011 register address 12 ro r/w 0 access status 0: register set to read/write 1: register set to read only 11 v1ui r/w 0 v1 undervoltage interrupts 0: no v1 undervoltage warning interrupt pending 1: v1 undervoltage warning interrupt pending 10 v2ui r/w 0 v2 undervoltage interrupts 0: no v2 undervoltage warning interrupt pending 1: v2 undervoltage warning interrupt pending 9 lwi r/w 0 lin wake-up interrupt 0: no lin wake-up interrupt pending 1: lin wake-up interrupt pending 8 reserved r 0 7 ci r/w 0 cyclic interrupt 0: no cyclic interrupt pending 1: cyclic interrupt pending 6 wi1 r/w 0 wake-up interrupt 1 0: no wake-up interrupt 1 pending 1: wake-up interrupt 1 pending 5 posi r/w 1 power-on status interrupt 0: no power-on interrupt pending 1: power-on interrupt pending 4 wi2 r/w 0 wake-up interrupt 2 0: no wake-up interrupt 2 pending 1: wake-up interrupt 2 pending 3 cwi r/w 0 can wake-up interrupt 0: no can wake-up interrupt pending 1: can wake-up interrupt pending 2:0 reserved r 000
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 17 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.4 watchdog (uja1075a /xx/wd versions) three watchdog modes are supported: window, timeout and off. the watchdog period is programmed via the nwp control bits in the wd_and_status register (see ta b l e 4 ). the default watchdog period is 128 ms. a watchdog trigger event is any write acce ss to the wd_and_status register. when the watchdog is triggered, the watchdog timer is reset. in watchdog window mode, a watchdog trigger event within a closed watchdog window (i.e. the first half of the window before t trig(wd)1 ) will generate an sbc re set. if the watchdog is triggered before the watchdog timer overflows in timeout or window mode, or within the open watchdog window (after t trig(wd)1 but before t trig(wd)2 ), the timer restarts immediately. the following watchdog events result in an immediate system reset: ? the watchdog overflows in window mode ? the watchdog is triggered in the first ha lf of the watchdog period in window mode ? the watchdog overflows in timeout mode while a cyclic interrupt (ci) is pending ? the state of the wdoff pin changes in normal mode or standby mode ? the watchdog mode control bit (wmc) changes state in normal mode after a watchdog rese t (short reset; see section 6.5.1 and ta b l e 11 ), the default watchdog period is selected (nwp = 100). the watchdog can be switched off completely by forcing pin wdoff high. the watchdog can also be s witched off by setting bit wmc to 1 in standby mode. if the watchdog was turned of f by setting wmc, any pending interrupt will re-enable it. note that the state of bit wmc cannot be c hanged in standby mode if an interrupt is pending. any attempt to change wmc wh en an interrupt is pending will be ignored. 6.4.1 watchdog window behavior the watchdog runs continuously in window mode. if the watchdog overflows, or is triggered in th e first half of the watchdog period (less than t trig(wd)1 after the start of the watchdog pe riod), a system reset will be performed. watchdog overflow occurs if the watchdog is not triggered within t trig(wd)2 after the start of the watchdog period. if the watchdog is triggered in the second half of the watchdog period (at least t trig(wd)1 , but not more than t trig(wd)2 , after the start of the watchdog period), the watchdog will be reset. the watchdog is in window mode when pin wdoff is low, the sbc is in normal mode and the watchdog mode control bit (wmc) is set to 0. 6.4.2 watchdog timeout behavior the watchdog runs continuously in timeout mode. it can be reset at any time by a watchdog trigger. if the watchdog overflows, the ci bit is set. if a ci is already pending, a system reset is performed. the watchdog is in timeout mode when pin wdoff is low and:
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 18 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip ? the sbc is in standby mode and bit wmc = 0 or ? the sbc is in normal mode and bit wmc = 1 6.4.3 watchdog off behavior the watchdog is disabled in this state. the watchdog is in off mode when: ? the sbc is in off, ov ertemp or sleep modes ? the sbc is in standby mode and bit wmc = 1 ? the sbc is in any mode and the wdoff pin is high 6.5 system reset the following events will cause the sbc to perform a system reset: ? v1 undervoltage (reset pulse length selected via external pull-up resistor on rstn pin) ? an external reset (p in rstn forced low) ? watchdog overflow (window mode) ? watchdog overflow in timeout mode with ci pending ? watchdog triggered too early in window mode ? wmc value changed in normal mode ? wdoff pin state changed ? sbc goes to sleep mode (mc set to 01; see ta b l e 5 ) while pin intn is driven low ? sbc goes to sleep mode (mc set to 01; see ta b l e 5 ) while stbcc = stbcl = wic1 = wic2 = 0 ? sbc goes to sleep mode (mc set to 01; see ta b l e 5 ) while wake-up pending ? software reset (swr = 1) ? sbc leaves overtemp mode (reset pulse length selected via external pull-up resistor on rstn pin) a watchdog overflow in timeout mode requests a ci, if a ci is not already pending. the uja1075a provides three signals for dealing with reset events: ? rstn pin input/output for performing a global ecu system reset or forcing an external reset ? en pin, a fail-safe global enable output ? limp pin, a fail-safe limp home output 6.5.1 rstn pin a system reset is triggered if the bidirecti onal rstn pin is forced low for at least t fltr by the microcontroller (external reset). a reset pulse is output on pin rstn by the sbc when a system reset is tr iggered internally.
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 19 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip the reset pulse width (t w(rst) ) is selectable (short or long) if the system reset was generated by a v1 undervoltage event (see section 6.6.2 ) or by the sbc leaving off (v bat > v th(det)pon ) or overtemp (temperature < t th(rel)otp ) modes. a short reset pulse is selected by connecting a 900 10 % resistor between pins rstn and v1. if a resistor is not connected, the reset pulse will be long (see ta b l e 11 ). in all other cases (e.g. watc hdog-related reset events) the reset pulse length will be short. 6.5.2 en output the en pin can be used to control external hardware, such as power components, or as a general-purpose output when the system is running properly. in normal and standby modes, the microcontro ller can set the en control bit (bit enc in the mode_control register; see table 5 ) via the spi inte rface. pin en will be high when enc = 1 and mc = 10 or 11. a reset event will ca use pin en to go low. en pin behavior is illustrated in figure 5 . 6.5.3 limp output the limp pin can be used to enable the so called ?limp home? hardware in the event of an ecu failure. detectable failure conditions include sbc overtemperature events, loss of watchdog service, pins rstn or v1 clampe d low and user-initiat ed or external reset events. the limp pin is a battery-related, active-low, open-drain output. a system reset will cause the limp home wa rning control bit (bit lhwc in the mode_control register; see table 5 ) to be set. if lhwc is al ready set when the system reset is generated, bit lhc will be set which will force the limp pin low. the application should clear lhwc after each reset event to ensure the limp output is not activated during normal operation. in overtemp mode, bit lhc is always set and, consequently, the limp output is always active. if the application manages to recover from the event that activated the limp output, lhc can be cleared to deactivate the limp output. fig 5. behavior of en pin rstn en enc mode standby normal standby 015aaa07 4
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 20 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.6 power supplies 6.6.1 battery pin (bat) the sbc contains a single supply pin, bat. an external diode is needed in series to protect the device against negative voltages. the operating range is from 4.5 v to 28 v. the sbc can handle maximum voltages up to 40 v. if the voltage on pin bat falls below the power-off detection threshold, v th(det)poff , the sbc immediately enters off mode, which means that the voltage regulators and the internal logic are shut down. the sbc leaves off mode for standby mode as soon as the voltage rises above the power-on detection threshold (v th(det)pon ). the posi bit in the int_status register is set to 1 when the sbc leaves off mode. 6.6.2 voltage regulator v1 voltage regulator v1 is intended to supply th e microcontroller, its periphery and additional transceivers. v1 is supplied by pin bat and delivers up to 250 ma at 3.3 v or 5 v (depending on the uja1075a version). to prevent the device overheating at high ambient temperatures or high average currents, an external pnp transistor can be connected as illustrated in figure 6 . in this configuration, the power dissipation is distributed between the sbc and the pnp transistor. bit pdc in the mode_control register ( ta b l e 5 ) is used to regulate how the power dissipation is distributed. if pdc = 0, the pnp transistor will be activated when the load current reaches 85 ma (50 ma if pdc = 1) at t vj =150 c. v1 will continue to deliver 85 ma while the transistor delivers the additional load current (see figure 7 and figure 8 ). fig 6. external pnp tran sistor control circuit uja1075a vexctrl v1 vexcc 015aaa181 bat battery
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 21 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip figure 7 illustrates how v1 and the pnp transistor combine to supply a slow ramping load current of 250 ma with pdc = 0. any addition al load current requ irement will be supplied by the pnp transistor, up to its current lim it. if the load current continues to rise, i v1 will increase above the selected pdc threshold (to a maximum of 250 ma). for a fast ramping load curren t, v1 will deliver the required load current (to a maximum of 250 ma) until the pnp transistor has switched on. once the transistor has been activated, v1 will deliver 85 ma (pdc = 0) with the transi stor contributing the balance of the load current (see figure 8 ). fig 7. v1 and pnp currents at a slow ramping load current of 250 ma (pdc = 0) fig 8. v1 and pnp currents at a fast ramping load current of 250 ma (pdc = 0) 015aaa11 1 250 ma 85 ma 50 ma load current 215 ma 165 ma pnp current i v1 i th(act)pnp = 85 ma (pdc = 0) i th(deact)pnp = 50 ma (pdc = 0) load current 250 ma ? 165 ma 0 ma i v1 165 ma 250 ma pnp current 015aaa075 i th(act)pnp = 85 ma (pdc = 0)
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 22 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip for short-circuit protection, a resistor needs to be connected between pins v1 and vexcc to allow the current to be monitored. this resistor limits th e current delivered by the external transistor. if the voltage difference between pins vexcc and v1 reaches v th(act)ilim , the pnp current limiting activation thre shold voltage, the tr ansistor current will not increase further. the thermal performance of th e transistor needs to be considered when calculating the value of this resistor. a 3.3 resistor was used with the bcp52-16 (nxp semiconductors) employed during testing. note that the selectio n of the transistor is not critical. in general, any pnp transistor with a curr ent amplification factor ( ) of between 60 and 500 can be used. if an external pnp transistor is not used, pin vexcc must be connected to v1 while pin vexctrl can be left open. one advantage of this scalable voltage regulato r concept is that there are no pcb layout restrictions when using the external pnp. the distance between the uja1075a and the external pnp doesn?t affect th e stability of the regulator loop because the loop is realized within the uja1075a. therefore, it is re commended that the distance between the uja1075a and pnp transistor be maxi mized for optimal thermal distribution. the output voltage on v1 is monitored continuously and a system reset signal is generated if an undervoltage event occurs. a system reset is generated if the voltage on v1 falls below the undervoltage detection voltage (v uvd ; see ta b l e 1 0 ). the reset threshold (90 % or 70 % of the nominal value) is set via the reset threshold control bit (rthc) in the int_control register ( ta b l e 6 ). in addition, an undervoltage warning (a v1ui interrupt) will be gene rated at 90 % of the nomi nal output voltage. the status of v1 can be read via bit v1s in the wd_and_status register ( ta b l e 4 ). 6.6.3 voltage regulator v2 voltage regulator v2 is reserved for the high-speed can transceiver, providing a 5 v supply. v2 can be activated and deactivated via th e mc bits in the mode_control register ( ta b l e 5 ). an undervoltage warning (a v2ui interrupt) is generated when the output voltage drops below 90 % of its nominal value. th e status of v2 can be read via bit v2s in the wd_and_status register ( ta b l e 4 ) in normal mode (v2s = 1 in all other modes). v2 can be deactivated (mc = 10) to allow the internal can transceiver to be supplied from an external source or from v1. the alternative voltage source must be connected to pin v2. all internal functions (e.g. unde rvoltage protection) will work normally. 6.7 can transceiver the analog section of the uja1075a can transc eiver corresponds to that integrated into the tja1042/tja1043. the transceiver is designed for high-speed (up to 1 mbit/s) can applications in the automotive industry, pr oviding differential transmit and receive capability to a can protocol controller. 6.7.1 can operating modes 6.7.1.1 active mode the can transceiver is in active mode when:
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 23 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip ? the sbc is in normal mode (mc = 10 or 11) ? the transceiver is enabled (bit stbcc = 0; see ta b l e 6 ) and ? v2 is enabled and its output voltage is above its undervoltage threshold, v uvd or ? v2 is disabled but an external voltage source, or v1, connected to pin v2 is above its undervoltage threshold (see section 6.6.3 ) in can active mode, the transceiver can tr ansmit and receive data via the canh and canl pins. the differential receiver converts the analog data on the bus lines into digital data which is output on pin rxdc. the transm itter converts digital data generated by a can controller, and input on pin txdc, to signals suitable for transmission over the bus lines. 6.7.1.2 lowpower/off modes the can transceiver will be in lowpower mode with bus wake-up detection enabled if bit stbcc = 1 (see table 6 ). the can transceiver can be woken up remotely via pins canh and canl in lowpower mode. when the sbc is in standby mode or sleep mode (mc = 00 or 01), the can transceiver will be in off mode if bit stbcc = 0. the ca n transceiver is powered down completely in off mode to minimize quiescent current consumption. a filter at the receiver input prevents unwanted wake-up events occurring due to automotive transients or elec tromagnetic inte rference (em)i. a recessive-dominant-recessi ve-dominant sequence must occur on the can bus within the wake-up time-out time (t to(wake) ) to pass the wake-up filter and trigger a wake-up event (see figure 9 ; note that additional pulses may occur between the recessive/dominant phases). the minimum recess ive/dominant bus times for can transceiver wake-up (t wake(busrec)min and t wake(busdom)min ) must be satisfied (see table 11 ). fig 9. can wake-up timing diagram recessive dominant recessive dominant wake-up 015aaa10 7 t wake < t to(wake)
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 24 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.7.2 split circuit pin split provides a dc stabilized voltage of 0.5v v2 . it is activated in can active mode only. pin split is floating in can lowpower and off modes. the v split circuit can be used to stabilize the recess ive common-mode voltage by c onnecting pin split to the center tap of the split termination (see figure 10 ). a transceiver in the network that is not supp lied and that generates a significant leakage current from the bus lines to ground, can result in a recessive bus voltage of < 0.5v v2 . in this event, the split circuit will stab ilize the recessive voltage at 0.5v v2 . so a start of transmission will not generate a step in the common-mode signal which would lead to poor electromagnetic emission (eme) performance. 6.7.3 fail-safe features 6.7.3.1 txdc dominant time-out function a txdc dominant time-out timer is started when pin txdc is forced low. if the low state on pin txdc persists for longer than the txdc dominant time-out time (t to(dom)txdc ), the transmitter will be disabled, releasing the bus lines to recessive state. this function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all netw ork communications). the txdc dominant time-out timer is reset when pin txdc goes high. the txdc dominant time-out time also defines the minimum possible bit rate of 10 kbit/s. 6.7.3.2 pull-up on txdc pin pin txdc has an internal pull-up towards v v1 to ensure a safe defined state in case the pin is left floating. 6.8 lin transceiver the analog sections of the uja1075a lin transc eiver is identical to that integrated into the tja1021. the transceiver is the interface between the lin master/slave protocol controller and the physical bus in a lin. it is primarily intended for in-vehic le sub-networks using baud rates from 1 kbd up to 20 kbd and is lin 2.0/lin 2.1/sae j2602 compliant. fig 10. stabilization circuitry an d application using the split pin uja1075a v2 canl split canh 60 60 r r gnd v split = 0.5 v cc in normal mode; otherwise floating 015aaa18 2
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 25 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.8.1 lin operating modes 6.8.1.1 active mode the lin transceiver will be in active mode when: ? the sbc is in normal mode (mc = 10 or 11) and ? the transceiver is enabled (stbcl = 0; see ta b l e 6 ) and ? the battery voltage (v bat ) is above the lin undervoltage recovery threshold, v uvr(lin) . in lin active mode, the transceiver can transmit and receive data via the lin bus pin. the receiver detects data streams on the lin bus pin (lin) and transfers them to the microcontroller via pin rxdl (see figure 1 ) - lin recessive is represented by a high level on rxdl, lin dominant by a low level. the transmit data streams of the protocol controller at the txdl input (pin txdl) are converted by the transmitter into bus signals wit h optimized slew rate and wave shaping to minimize eme. 6.8.1.2 lowpower/off modes the lin transceiver will be in lowpower mode with bus wa ke-up detection enabled if bit stbcl = 1 (see ta b l e 6 ). the lin transceiver can be woken up remotely via pin lin in lowpower mode. when the sbc is in standby mode or sleep mode (mc = 00 or 01), the lin transceiver will be in off mode if bit stbcl = 0. the lin transceiver is powered down completely in off mode to minimize quiescent current consumption. filters at the receiver inputs prevent unwanted wake-up events due to automotive transients or emi. the wake-up event must remain valid for at least the minimum dominant bus time for wake-up of the lin transceiver, t wake(busdom)min (see ta b l e 11 ). 6.8.2 fail-safe features 6.8.2.1 general fail-safe features the following fail-safe features have been implemented: ? pin txdl has an internal pull-up towards v v1 to guarantee a safe, defined state if this pin is left floating ? the current of the transmitter output stage is limited in order to protect the transmitter against short circuits to pin bat ? a loss of power (pins bat and gnd) has no impact on the bus lines or on the microcontroller. there will be no re verse currents from the bus. 6.8.2.2 txdl dominant time-out function a txdl dominant time-out timer circuit prevent s the bus lines being driven to a permanent dominant state (blocking all network communica tions) if txdl is forced permanently low by a hardware and/or software application failure. the timer is triggered by a negative
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 26 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip edge on pin txdl. if the pin remains low for longer than the txdl dominant time-out time (t to(dom)txdl ), the transmitter is disabled, drivin g the bus lines to a recessive state. the timer is reset by a positive edge on the txdl pin. 6.9 local wake-up input the sbc provides 2 local wa ke-up pins (wake1 and wake 2). the edge sensitivity (falling, rising or both) of t he wake-up pins can be configur ed independently via the wic1 and wic2 bits in the int_control register ta b l e 6 ). these bits can also be used to disable wake-up via the wake-up pins. when wake-up is enabled, a valid wake-up event on either of these pins will cause a wake -up interrupt to be generated in standby mode or normal mode. if the sbc is in sleep mode when the wake-up event occurs, it will wake up and enter standby mode. the status of the wake-up pins can be read via the wake-up level status bits (wls1 and wls2) in the wd_and_status register ( table 4 ). note that bits wls1 and wls2 are only active when at least one of the wake up interrupts is enabled (wic1 00 or wic2 00). the sampling of the wake-up pins can be synchronized with the wbias signal by setting bits wse1 and wse2 in the int_control register to 1 (if wsex = 0, wake-up pins are sampled continuously). the sampling will be performed on th e rising edge of wbias (see figure 11 ). the sampling time, 16 ms or 64 ms, is selected via the wake bias control bit (wbc) in the mode_control register. figure 12 shows a typical circuit for implementing cyclic sampling of the wake-up inputs. fig 11. wake-up pin sampling synchronized with wbias signal wake-up int wakex pin wbias pin wbiasi (internal) enable bias disable bias disable bias wake level latched 015aaa07 8
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 27 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 6.10 interrupt output pin intn is an active-low, open-drain interrupt output. it is driven low when at least one interrupt is pending. an interrupt can be cleared by writing 1 to the corresponding bit in the int_status register ( ta b l e 7 ). clearing bits lwi and cwi in standby mode only clears the interrupt status bits and not the pending wake-up. the pending wake-up is cleared on entering normal mode and when the corresponding standby control bit (stbcc or stbcl) is 0. on devices that contain a watchdog, the ci is enabled when the watchdog switches to timeout mode while the sbc is in standby mode or normal mode (provided pin wdoff = low). a ci is generated if the watchdog overflows in timeout mode. the ci is provided to alert the microcontroller when the watchdog overflows in timeout mode. the ci will wake up the microcontroller from a c standby mode. after polling the int_status register, the microcontroller will be aw are that the ap plication is in cyclic wake up mode. it can then perform some checks on can and lin before returning to the c standby mode. 6.11 temperature protection the temperature of the sbc chip is monitored in normal and standby modes. if the temperature is too high, the sb c will go to overtemp mode, where the rstn pin is driven low and limp home is activated. in addition, the voltage regulators and the can and lin transmitters are switched off (see also section 6.1.6 ? overtemp mode ? ). when the temperature falls belo w the temperature shut down threshold, the sbc will go to standby mode. the temperature shutdown threshold is between 165 c and 200 c. fig 12. typical application for cyc lic sampling of wake-up signals uja1075a wake1 wake2 bat wbias 015aaa18 3 47 k 47 k pdta144e t sample of wakex sample of wakex sample of wakex gnd biasing of switches
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 28 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 7. limiting values table 8. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v x voltage on pin x dc value pins v1, v2 and intn ? 0.3 7 v pins txdc, rxdc, en, sd i, sdo, sck, scsn, txdl, rxdl, rstn and wdoff ? 0.3 v v1 + 0.3 v pin vexcc v v1 ? 0.3 v v1 + 0.35 v pins wake1, wake2 and wb ias; with respect to any other pin ? 58 +58 v pin limp and bat ? 0.3 +40 v pin vexctrl ? 0.3 v bat + 0.3 v pins canh, canl, split and lin; with respect to any other pin ? 58 +58 v pin dlin; with respect to any other pin v bat ? 0.3 +58 v i r(v1-bat) reverse current from pin v1 to pin bat v v1 5v [1] - 250 ma i dlin current on pin dlin ? 65 0 ma v trt transient voltage on pins bat: via reverse polarity diode/capacitor canl, canh, split: coupling with two capacitors on the bus lines lin: coupling via 1 nf capacitor dlin: via 1 k resistor [2] ? 150 +100 v v esd electrostatic discharge voltage iec 61000-4-2 [3] pins bat with capacitor, canh, canl and lin; via a series resistor on pins split, dlin, wake1 and wake2 [4] ? 6+6kv hbm [5] pins canh, canl, lin, split, dlin, wake1 and wake2 [6] ? 8+8kv pin bat; referenced to ground ? 4+4kv pin test2; referenced to pin bat ? 1.25 +2 kv pin test2; referenced to other reference pins ? 2+2kv any other pin ? 2+2kv mm [7] any pin ? 300 +300 v cdm [8] corner pins ? 750 +750 v any other pin ? 500 +500 v t vj virtual junction temperature [9] ? 40 +150 c t stg storage temperature ? 55 +150 c
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 29 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip [1] a reverse diode connected between v1 (anode) and bat (cathode) limits the voltage drop voltage from v1(+) to bat (-). [2] verified by an external test house to ensure pins can withst and iso 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. [3] iec 61000-4-2 (150 pf, 330 ) . [4] esd performance according to iec 61000-4-2 (150 pf, 330 ) has been verified by an external test house for pins bat, canh, canl, lin, wake1 and wake2. the result is equal to or better than 6 kv. [5] human body model (hbm): according to aec-q100-002 (100 pf, 1.5 k ). [6] v1, v2 and bat connected to gnd, emulating application circuit. [7] machine model (mm): according to aec-q100-003 (200 pf, 0.75 h, 10 ). [8] charged device model (cdm): according to aec-q100-011 (field induced charge; 4 pf). [9] in accordance with iec 60747-1. an alternative definition of virtual junction temperature is: t vj =t amb +p r th(vj-a) , where r th(vj-a) is a fixed value to be used for the calculation of t vj . the rating for t vj limits the allowable combinations of power dissipation (p) and ambient temperature (t amb ). t amb ambient temperature ? 40 +125 c table 8. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 30 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 8. thermal characteristics layout conditions for r th(j-a) measurements: board finish thickness 1.6 mm 10 %, double-layer board, board dimensions 129 mm 60 mm, board material fr4, cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm 0.08 mm, cu thickness on vias 0.025 mm. optional heat sink top layer of 3.5 mm 25 mm will reduce thermal resistance (see figure 14 ). fig 13. htssop pcb pcb copper area: (bottom layer) 2 cm 2 pcb copper area: (bottom layer) 8 cm 2 015aaa137 optional heatsink top layer optional heatsink top layer optional heatsink top layer
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 31 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip [1] according to jedec jesd51-2 and jesd 51-3 at natural convection on 1s board. [2] according to jedec jesd51-2, jesd51-5 and jesd51 -7 at natural convection on 2s2p board. board with two inner copper layers (thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer. fig 14. htssop32 thermal resistance junction to ambient as a function of pcb copper area table 9. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient single-layer board [1] 78 k/w four-layer board [2] 39 k/w pcb cu heatsink area (cm 2 ) 0 10 8 46 2 015aaa138 50 70 90 r th(j-a) (k/w) 30 without heatsink top layer with heatsink top layer
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 32 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 9. static characteristics table 10. static characteristics t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit supply; pin bat v bat battery supply voltage 4.5 - 28 v i bat battery supply current mc = 00 (standby; v1 on, v2 off) stbcc = stbcl = 1 (can/lin wake-up enabled) wic1 = wic2 = 11 (wake interrupts enabled); 7.5 v < v bat <28v i v1 =0ma; v rstn = v scsn =v v1 v txdl =v txdc =v v1 ; v sdi =v sck =0v t vj = ? 40 c-8398 a t vj =25 c-7688 a t vj = 150 c-6880 a mc = 01 (sleep; v1 off, v2 off) stbcc = stbcl = 1 (can/lin wake-up enabled) wic1 = wic2 = 11 (wake interrupts enabled) 7.5 v < v bat <28v; v v1 =0v t vj = ? 40 c-6071 a t vj =25 c-5665 a t vj = 150 c-5159 a contributed by lin wake-up receiver stbcl = 1 v lin =v bat 5.5 v < v bat <28v -1.12 a contributed by can wake-up receiver stbcc = 1; v canh =v canl =2.5v 5.5 v < v bat <28v 1613 a contributed by wakex pin edge detectors wic1 = wic2 = 11 v wake1 =v wake2 =v bat 0510 a
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 33 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip i bat(add) additional battery supply current 5.1 v < v bat <7.5v - - 50 a 4.5 v < v bat <5.1v v1 on (5 v version) --3 ma v2 on; mc = 11 v2uie = 1; i v2 = 0 ma 100 - 950 a can active mode (recessive) stbcc = 0; mc = 1x; v txdc =v v1 i canh = i canl = 0 ma 5.5 v < v bat <28v --10ma can active (dominant) stbcc = 0; mc = 1x; v txdc =0v r (canh-canl) =45 5.5 v < v bat <28v --70ma lin active mode (recessive) stbcl = 0; mc = 1x v txdl =v v1 ; i dlin =i lin = 0 ma 5.5 v < v bat <28v - - 1300 a lin active mode (dominant); stbcl = 0; mc = 1x v txdl =0 v; i dlin =i lin = 0 ma v bat =14v --5 ma lin active mode (dominant) stbcl = 0; mc = 1x; v bat =28v v txdl =0 v; i dlin =i lin = 0 ma --10ma v th(det)pon power-on detection threshold voltage 4.5 - 5.5 v v th(det)poff power-off detection threshold voltage 4.25 - 4.5 v v hys(det)pon power-on detection hysteresis voltage 200 - - mv v uvd(lin) lin undervoltage detection voltage 5- 5.3v v uvr(lin) lin undervoltage recovery voltage 5- 5.5v v hys(uvd)lin lin undervoltage detection hysteresis voltage 25 - 300 mv v uvd(ctrl)iext external current control undervoltage detection voltage 5.9 - 7.5 v table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 34 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip voltage source; pin v1 v o output voltage v o(v1)nom = 5 v; v bat = 5.5 v to 28 v i v1 = ? 200 ma to ? 5 ma 4.9 5 5.1 v v o(v1)nom = 5 v; v bat = 5.5 v to 28 v i v1 = ? 250 ma to ? 200 ma 4.75 5 5.1 v v o(v1)nom = 5 v; v bat = 5.5 v to 5.75 v i v1 = ? 250 ma to ? 5 ma 150 c< t vj <200 c 4.5 5 5.1 v v o(v1)nom = 5 v; v bat = 5.75 v to 28 v i v1 = ? 250 ma to ? 5 ma 150 c< t vj <200 c 4.85 5 5.1 v v o(v1)nom = 3.3 v; v bat = 4.5 v to 28 v i v1 = ? 250 ma to ? 5 ma 3.234 3.3 3.366 v v o(v1)nom = 3.3 v; v bat = 4.5 v to 28 v i v1 = ? 250 ma to ? 5 ma 150 c< t vj <200 c 2.97 3.3 3.366 v r (bat-v1) resistance between pin bat and pin v1 v o(v1)nom = 5 v; v bat = 4.5 v to 5.5 v i v1 = ? 250 ma to ? 5 ma regulator in saturation --3 v uvd undervoltage detection voltage 90 %; v o(v1)nom = 5 v; rthc = 0 4.5 - 4.75 v 90 %; v o(v1)nom = 3.3 v; rthc = 0 2.97 - 3.135 v 70 %; v o(v1)nom = 5 v; rthc = 1 3.5 - 3.75 v v uvr undervoltage recovery voltage 90 %; v o(v1)nom = 5 v 4.56 - 4.9 v 90 %; v o(v1)nom = 3.3 v 3.025 - 3.234 v i o(sc) short-circuit output current i vexcc = 0 ma ? 600 - ? 250 ma load regulation v v1 voltage variation on pin v1 as a function of load current variation v bat = 5.75 v to 28 v i v1 = ? 250 ma to ? 5 ma --25mv line regulation v v1 voltage variation on pin v1 as a function of supply voltage variation v bat = 5.5 v to 28 v; i v1 = ? 30 ma --25mv pnp base; pin vexctrl i o(sc) short-circuit output current v vexctrl 4.5 v; v bat = 6 v to 28 v 3.5 5.8 8 ma i th(act)pnp pnp activation threshold current load current increasing; external pnp transistor connected - see section 6.6.2 pdc 0 74 130 191 ma pdc 0; t vj =150 c748599ma pdc 1 44 76 114 ma pdc 1; t vj =150 c445059ma table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 35 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip i th(deact)pnp pnp deactivation threshold current load current falling; external pnp transistor connected - see section 6.6.2 pdc 0 40 76 120 ma pdc 0; t vj =150 c445059ma pdc 1 11 22 36 ma pdc 1; t vj =150 c121518ma pnp collector; pin vexcc v th(act)ilim current limiting activation threshold voltage measured across resistor connected between pins vexcc and v1 (see section 6.6.2 ) 2.97 v v v1 5.5 v 6v < v bat < 28 v 240 - 330 mv voltage source; pin v2 v o output voltage v bat = 5.5 v to 28 v i v2 = ? 100 ma to 0 ma 4.75 5 5.25 v v bat = 6 v to 28 v i v2 = ? 120 ma to 0 ma 4.75 5 5.25 v v v2 voltage variation on pin v2 as a function of supply voltage variation v bat = 5.5 v to 28 v i v2 = ? 10 ma --60mv as a function of load current variation; 6v < v bat < 28 v i v2 = ? 100 ma to ? 5ma --80mv v uvd undervoltage detection voltage 4.5 - 4.70 v v uvr undervoltage recovery voltage 4.55 - 4.75 v v uvhys undervoltage hysteresis voltage 20 - 80 mv i o(sc) short-circuit output current v v2 = 0 v to 5.5 v ? 250 - ? 100 ma serial peripheral interface inputs; pins sdi, sck and scsn v th(sw) switching threshold voltage v v1 = 2.97 v to 5.5 v 0.3v v1 -0.7v v1 v v hys(i) input hysteresis voltage v v1 = 2.97 v to 5.5 v 100 - 900 mv r pd(sck) pull-down resistance on pin sck 50 130 400 k r pu(scsn) pull-up resistance on pin scsn 50 130 400 k i li(sdi) input leakage current on pin sdi ? 5- +5 a serial peripheral interface data output; pin sdo i oh high-level output current v scsn = 0 v; v o = v v1 ? 0.4 v v v1 = 2.97 v to 5.5 v ? 30 - ? 1.6 ma i ol low-level output current v scsn = 0 v; v o = 0.4 v v v1 = 2.97 v to 5.5 v 1.6 - 30 ma table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 36 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip i lo output leakage current v scsn = v v1 ; v o = 0 v to v v1 v v1 = 2.97 v to 5.5 v ? 5- 5 a reset output with clamping detection; pin rstn i oh high-level output current v rstn = 0.8v v1 v v1 = 2.97 v to 5.5 v ? 1500 - ? 100 a i ol low-level output current strong; v rstn = 0.2v v1 v v1 = 2.97 v to 5.5 v ? 40 c< t vj < 200 c 4.9 - 40 ma weak; v rstn =0.8v v1 v v1 = 2.97 v to 5.5 v ? 40 c< t vj < 200 c 200 - 540 a v ol low-level output voltage v v1 = 1 v to 5.5 v pull-up resistor to v v1 900 ? 40 c< t vj < 200 c; v bat < 28 v 0 - 0.2v v1 v v v1 = 2.975 v to 5.5 v pull-up resistor to v1 900 ; ? 40 c< t vj <200 c 0- 0.5v v oh high-level output voltage -40 c< t vj <200 c0.8v v1 -v v1 + 0.3 v v th(sw) switching threshold voltage v v1 = 2.97 v to 5.5 v 0.3v v1 -0.7v v1 v v hys(i) input hysteresis voltage v v1 = 2.97 v to 5.5 v 100 - 900 mv interrupt output; pin intn i ol low-level output current v ol = 0.4 v 1.6 - 15 ma enable output; pin en i oh high-level output current v oh = v v1 ? 0. 4 v v v1 = 2.97 v to 5.5 v ? 20 - ? 1.6 ma i ol low-level output current v ol = 0.4 v; v v1 = 2.97 v to 5.5 v 1.6 - 20 ma v ol low-level output voltage i ol = 20 a; v v1 = 1.5 v - - 0.4 v watchdog off input; pin wdoff v th(sw) switching threshold voltage v v1 = 2.97 v to 5.5 v 0.3v v1 -0.7v v1 v v hys(i) input hysteresis voltage v v1 = 2.97 v to 5.5 v 100 - 900 mv r pupd pull-up/pull-down resistance v v1 = 2.97 v to 5.5 v 5 10 20 k wake input; pin wake1, wake2 v th(sw) switching threshold voltage 2 - 3.75 v v hys(i) input hysteresis voltage 100 - 1000 mv i pu pull-up current v wake = 0 v for t < t wake ? 2- 0 a i pd pull-down current v wake = v bat for t < t wake 0- 2 a limp home output; pin limp i o output current v limp = 0.4 v; lhc = 1 t vj = ? 40 c to 200 c 0.8 - 8 ma wake bias output; pin wbias i o output current v wbias = 1.4 v 1 - 7 ma table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 37 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip can transmit data input; pin txdc v th(sw) switching threshold voltage v v1 = 2.97 v to 5.5 v 0.3v v1 -0.7v v1 v v hys(i) input hysteresis voltage v v1 = 2.97 v to 5.5 v 100 - 900 mv r pu pull-up resistance 4 12 25 k can receive data output; pin rxdc i oh high-level output current can active mode v rxdc = v v1 ? 0.4 v ? 20 - ? 1.5 ma i ol low-level output current v rxdc = 0.4 v 1.6 - 20 ma r pu pull-up resistance mc = 00; standby mode 4 12 25 k high-speed can bus lines; pins canh and canl v o(dom) dominant output voltage can active mode v v2 = 4.5 v to 5.5 v; v txdc = 0 v r (canh-canl) = 60 pin canh 2.75 3.5 4.5 v pin canl 0.5 1.5 2.25 v v dom(tx)sym transmitter dominant voltage symmetry v dom(tx)sym = v v2 ? v canh ? v canl r (canh-canl) = 60 ? 400 - +400 mv v o(dif)bus bus differential output voltage can active mode (dominant) v v2 = 4.75 v to 5.25 v; v txdc = 0 v r (canh-canl) = 45 to 65 1.5 - 3.0 v can active mode (recessive) v v2 = 4.5 v to 5.5 v; v txdc = v v1 r (canh-canl) = no load ? 50 0 +50 mv v o(rec) recessive output voltage can active mode; v v2 = 4.5 v to 5.5 v v txdc = v v1 r (canh-canl) = no load 20.5v v2 3v can lowpower/off mode r (canh-canl) = no load ? 0.1 - +0.1 v i o(dom) dominant output current can active mode v txdc =0v; v v2 = 5 v pin canh; v canh =0v ? 100 ? 70 ? 40 ma pin canl; v canl = 40 v 40 70 100 ma i o(rec) recessive output current v canl = v canh = ? 27 v to +32 v v txdc = v v1 ; v v2 = 4.5 v to 5.5 v ? 3- +3 ma v th(rx)dif differential receiver threshold voltage can active mode v v2 = 4.5 v to 5.5 v ? 30 v < v canh < +30 v ? 30 v < v canl < +30 v 0.5 0.7 0.9 v can lowpower mode ? 12 v < v canh < +12 v ? 12 v < v canl < +12 v 0.4 0.7 1.15 v table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 38 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip v hys(rx)dif differential receiver hysteresis voltage can active mode v v2 = 4.5 v to 5.5 v ? 30 v < v canh < +30 v ? 30 v < v canl < +30 v 40 120 400 mv r i(cm) common-mode input resistance can active mode; v v2 = 5 v v canh = v canl = 5 v 91528k r i input resistance deviation can active mode; v v2 = 5 v v canh = v canl =5v ? 1- +1 % r i(dif) differential input resistance can active mode; v v2 = 5.5 v v canh = v canl = ? 35 v to +35 v 19 30 52 k c i(cm) common-mode input capacitance can active mode; not tested - - 20 pf c i(dif) differential input capacitance can active mode; not tested - - 10 pf i li input leakage current v bat = 0 v; v v2 = 0 v v canh = v canl =5v ? 5 - +5 a can bus common mode stabilization output; pin split v o output voltage can active mode v v2 = 4.5 v to 5.5 v i split = ? 500 a to 500 a 0.3v v2 0.5v v2 0.7v v2 v can active mode v v2 = 4.5 v to 5.5 v; r l 1m 0.45 v v2 0.5 v v2 0.55 v v2 v i l leakage current can lowpower/off mode or active mode with v v2 < 4.5 v v split = ? 30 v to + 30 v ? 5- +5 a lin transmit data input; pin txdl v th(sw) switching threshold voltage v v1 = 2.97 v to 5.5 v 0.3v v1 -0.7v v1 v v hys(i) input hysteresis voltage v v1 = 2.97 v to 5.5 v 100 - 900 mv r pu pull-up resistance 4 12 25 k lin receive data output; pin rxdl i oh high-level output current lin active mode v rxdl = v v1 ? 0.4 v ? 20 - ? 1.5 ma i ol low-level output current v rxdl = 0.4 v 1.6 - 20 ma r pu pull-up resistance mc = 00; standby mode 4 12 25 k lin bus line; pin lin i bus_lim current limitation for driver dominant state lin active mode v bat = v lin = 18 v v txdl = 0 v 40 - 100 ma i bus_pas_rec receiver recessive input leakage current v lin = 28 v; v bat = 5.5 v; v txdl = v v1 [1] --2 a i bus_pas_dom receiver dominant input leakage current including pull-up resistor v txdl = v v1 ; v lin = 0 v; v bat = 14 v ? 10 - +10 a i l(log) loss of ground leakage current v bat = v gnd =28v; v lin = 0 v ? 100 - 10 a table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 39 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip [1] guaranteed by design. i l(lob) loss of battery leakage current v bat = 0 v; v lin = 28 v [1] --2 a v rec(rx) receiver recessive voltage v bat = 5.5 v to 18 v 0.6 v bat -- v v dom(rx) receiver dominant voltage v bat = 5.5 v to 18 v - - 0.4v bat v v th(cntr)rx receiver center threshold voltage v th(cntr)rx =(v th(rec)rx + v th(dom)rx )/2 v bat = 5.5 v to 18 v; lin active mode 0.475 v bat 0.5 v bat 0.525 v bat v v th(hys)rx receiver hysteresis threshold voltage v th(hys)rx =v th(rec)rx ? v th(dom)rx v bat = 5.5 v to 18 v; lin active mode 0.05 v bat 0.15 v bat 0.175 v bat v c ext external capacitance on pin lin - - 30 pf v o(dom) dominant output voltage v txdl = 0 v; v bat = 7 v lin active mode --1.4v v txdl = 0 v; v bat = 18 v lin active mode --2.0v lin bus termination; pin dlin v (dlin-bat) voltage difference between pin dlin and pin bat 5ma < i dlin < 20 ma 0.4 0.65 1 v temperature protection t th(act)otp overtemperature protection activation threshold temperature 165 180 200 c t th(rel)otp overtemperature protection release threshold temperature 126 138 150 c table 10. static characteristics ?continued t vj = ? 40 c to +150 c; v bat =4.5v to 28v; v bat > v v1 ; v bat > v v2 ; r lin = 500 ; r (canh-canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 40 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 10. dynamic characteristics table 11. dynamic characteristics t vj = ? 40 c to +150 c; v bat = 4.5 v to 28 v; v bat > v v1 ; v bat > v v2 ; r lin =500 ; r (canh- canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit voltage source; pin v1 t d(uvd) undervoltage detection delay time v v1 falling; dv v1 /dt = 0.1 v/ s7-23 s t det(cl)l low-level clamping detection time v v1 <0.9v o(v1)nom ; v1 active 95 - 140 ms voltage source; pin v2 t d(uvd) undervoltage detection delay time v v2 falling, dv v2 /dt = 0.1 v/us 7 - 23 s serial peripheral interface timing; pins scsn, sck, sdi and sdo t cy(clk) clock cycle time v v1 = 2.97 v to 5.5 v 320 - - ns t spilead spi enable lead time v v1 = 2.97 v to 5.5 v; clock is low when spi select falls 110 - - ns t spilag spi enable lag time v v1 = 2.97 v to 5.5 v; clock is low when spi select rises 140 - - ns t clk(h) clock high time v v1 = 2.97 v to 5.5 v 160 - - ns t clk(l) clock low time v v1 = 2.97 v to 5.5 v 160 - - ns t su(d) data input set-up time v v1 = 2.97 v to 5.5 v 0 - - ns t h(d) data input hold time v v1 = 2.97 v to 5.5 v 80 - - ns t v(q) data output valid time pin sdo; v v1 = 2.97 v to 5.5 v c l = 100 pf --110ns t wh(s) chip select pulse width high v v1 = 2.97 v to 5.5 v 20 - - ns reset output; pin rstn t w(rst) reset pulse width long; r pu(rstn) > 25 k 20 - 25 ms short; r pu(rstn) = 900 to 1100 3.6 - 5 ms t det(cl)l low-level clamping detection time rstn driven high internally but pin rstn remains low 95 - 140 ms t fltr filter time 7 - 18 s watchdog off input; pin wdoff t fltr filter time 0.9 - 2.3 ms wake input; pin wake1, wake2 t wake wake-up time 10 - 40 s t d(po) power-on delay time 113 - 278 s can transceiver timi ng; pins canh, canl, txdc and rxdc t d(txdch-rxdch) delay time from txdc high to rxdc high 50 % v txdc to 50 % v rxdc v v2 = 4.5 v to 5.5 v r (canh-canl) = 60 c (canh-canl) = 100 pf; c rxdc = 15 pf f txdc = 250 khz 60 - 235 ns
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 41 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip t d(txdcl-rxdcl) delay time from txdc low to rxdc low 50 % v txdc to 50 % v rxdc v v2 = 4.5 v to 5.5 v r (canh-canl) = 60 c (canh-canl) = 100 pf; c rxdc = 15 pf f txdc = 250 khz 60 - 235 ns t d(txdc-busdom) delay time from txdc to bus dominant v v2 = 4.5 v to 5. 5 v r (canh-canl) = 60 c (canh-canl) = 100 pf -70- ns t d(txdc-busrec) delay time from txdc to bus recessive v v2 = 4.5 v to 5.5 v r (canh-canl) = 60 c (canh-canl) = 100 pf -90- ns t d(busdom-rxdc) delay time from bus dominant to rxdc v v2 = 4.5 v to 5.5 v r (canh-canl) = 60 c (canh-canl) = 100 pf c rxdc = 15 pf -75- ns t d(busrec-rxdc) delay time from bus recessive to rxdc v v2 = 4.5 v to 5.5 v r (canh-canl) = 60 c (canh-canl) = 100 pf c rxdc = 15 pf -95- ns t wake(busdom)min minimum bus dominant wake-up time first pulse (after first recessive) for wake-up on pins canh and canl sleep mode 0.5 - 3 s second pulse for wake-up on pins canh and canl 0.5 - 3 s t wake(busrec)min minimum bus recessive wake-up time first pulse for wake-up on pins canh and canl; sleep mode 0.5 - 3 s second pulse (after first dominant) for wake-up on pins canh and canl 0.5 - 3 s t to(wake) wake-up time-out time between wake-up and confirm messages; sleep mode 0.4 - 1.2 ms t to(dom)txdc txdc dominant time-out time can online; v v2 = 4.5v to 5.5v v txdc = 0 v 1.8 - 4.5 ms lin transceiver; pins lin, txdl, rxdl 1 duty cycle 1 v th(rec)rx(max) = 0.744v bat v th(dom)rx(max) = 0.581v bat ; t bit = 50 s v bat = 7 v to 18 v; lsc = 0 [1] [2] 0.396 - - % v th(rec)rx(max) = 0.76v bat v th(dom)rx(max) = 0.593v bat ; t bit = 50 s v bat = 5.5 v to 7 v; lsc = 0 [1] [2] 0.396 - - % 2 duty cycle 2 v th(rec)rx(min) = 0.422v bat v th(dom)rx(min) = 0.284v bat; t bit = 50 s v bat = 7.6 v to 18 v; lsc = 0 [2] [3] - - 0.581 % v th(rec)rx(min) = 0.41v bat v th(dom)rx(min) = 0.275v bat ; t bit = 50 s v bat = 6.1 v to 7.6 v; lsc = 0 [2] [3] - - 0.581 % table 11. dynamic characteristics ?continued t vj = ? 40 c to +150 c; v bat = 4.5 v to 28 v; v bat > v v1 ; v bat > v v2 ; r lin =500 ; r (canh- canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 42 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip [1] . variable t bus(rec)(min) is illustrated in the lin timing diagram in figure 18 . [2] bus load conditions are: c l = 1 nf and r l =1k ; c l = 6.8 nf and r l = 660 ; c l = 10 nf and r l = 500 . [3] . variable t bus(rec)(max) is illustrated in the lin timing diagram in figure 18 . [4] t pd(rx)sym =t pd(rx)r ? t pd(rx)f . [5] a system reset will be performed if the watchdog is in window mode and is triggered less than t trig(wd)1 after the start of the watchdog period (or in the first half of the watchdog period). [6] the nominal watchdog period is programmed via the nw p control bits in the wd_and_status register (see ta b l e 4 ); valid in watchdog window mode only. 3 duty cycle 3 v th(rec)rx(max) = 0.778v bat v th(dom)rx(max) = 0.616v bat t bit = 96 s; v bat = 7 v to 18 v; lsc = 1 [1] [2] 0.417 - - % v th(rec)rx(max) = 0.797v bat v th(dom)rx(max) = 0.630v bat t bit = 96 s; v bat = 5.5v to 7v; lsc=1 [1] [2] 0.417 - - % 4 duty cycle 4 v th(rec)rx(min) = 0.389v bat v th(dom)rx(min) = 0.251v bat; t bit = 96 s v bat = 7.6 v to 18 v; lsc = 1 [2] [3] - - 0.590 % v th(rec)rx(min) = 0.378v bat v th(dom)rx(min) = 0.242v bat ; t bit = 96 s v bat = 6.1 v to 7.6v; lsc = 1 [2] [3] - - 0.590 % t pd(rx)r rising receiver propagation delay v bat = 5.5 v to 18 v; r rxdl = 2.4 k c rxdl = 20 pf --6 s t pd(rx)f falling receiver propagation delay v bat = 5.5 v to 18 v; r rxdl = 2.4 k c rxdl = 20 pf --6 s t pd(rx)sym receiver propagation delay symmetry v bat = 5.5 v to 18 v; r rxdl = 2.4 k c rxdl = 20 pf [4] ? 2-+2 s t wake(busdom)min minimum bus dominant wake-up time 28 - 104 s t to(dom)txdl txdl dominant time-out time lin online mode; v txdl = 0 v 20 - 80 ms wake bias output; pin wbias t wbiasl wbias low time 227 - 278 s t cy cycle time wbc = 1 58.1 - 71.2 ms wbc = 0 14.5 - 17.8 ms watchdog t trig(wd)1 watchdog trigger time 1 normal mode watchdog window mode only [5] 0.45 nwp [6] - 0.555 nwp [6] ms t trig(wd)2 watchdog trigger time 2 normal, standby and sleep modes watchdog window mode only [7] 0.9 nwp [6] -1.11 nwp [6] ms oscillator f osc oscillator frequency 460.8 512 563.2 khz table 11. dynamic characteristics ?continued t vj = ? 40 c to +150 c; v bat = 4.5 v to 28 v; v bat > v v1 ; v bat > v v2 ; r lin =500 ; r (canh- canl) = 45 to 65 ; all voltages are defined with respect to ground; positive current s flow in the ic; typical values are given at v bat = 14 v; unless otherwise specified. symbol parameter conditions min typ max unit 1 3 , t bus rec () min () 2t bit ------------------------------- = 2 4 , t bus rec () max () 2t bit -------------------------------- =
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 43 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip [7] the watchdog will be reset if it is in window mode and is triggered at least t trig(wd)1 , but not more than t trig(wd)2 , after the start of the watchdog period (or in the second half of the watchdog period). a system reset will be performed if the watchdog is triggered m ore than t trig(wd)2 after the start of the watchdog period (watchdog overflows). fig 15. timing test circuit for can transceiver fig 16. can transceiver timing diagram sbc bat canl canh txdc r canh ? r canl rxdc c rxdc gnd c canh ? c canl 015aaa079 canh canl t d(txdc-busdom) txdc v o(dif)bus rxdc high high low low dominant recessive 0.9 v 0.5 v t d(busdom-rxdc) t d(txdc-busrec) t d(busrec-rxdc) t d(txdch-rxdch) t d(txdcl-rxdcl) 015aaa15 1
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 44 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip fig 17. timing test circuit for lin transceiver sbc bat dlin txdl r lin c lin rxdl c rxdl lin gnd 015aaa20 4 fig 18. lin transceiver timing diagram 015aaa133 v txdl lin bus signal v bat t bit t bus(rec)(min) v th(rec)rx(max) thresholds of receiving node a v th(dom)rx(max) v th(rec)rx(min) v th(dom)rx(min) t pd(rx)r t pd(rx)f t pd(rx)r t pd(rx)f t bus(rec)(max) t bit t bit thresholds of receiving node b output of receiving node a v rxdl output of receiving node b v rxdl t bus(dom)(max) t bus(dom)(min)
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 45 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 11. test information 11.1 quality information this product has been qualified in accordance with the automotive electronics council (aec) standard q100 - failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications. fig 19. spi timing diagram 015aaa04 5 scsn sck sdi sdo x x x msb lsb msb lsb t v(q) floating floating t h(d) t su(d) t clk(l) t clk(h) t spilead t cy(clk) t spilag t wh(s)
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 46 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 12. package outline fig 20. package outline sot549-1 (htssop32) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot549-1 03-04-07 05-11-02 w m a a 1 a 2 e h d h d l p detail x e z exposed die pad side e c l x (a 3 ) 0.25 1 16 32 17 y b h e 0.95 0.85 0.30 0.19 d h 5.1 4.9 e h 3.6 3.4 0.20 0.09 11.1 10.9 6.2 6.0 8.3 7.9 0.65 1 0.2 0.78 0.48 0.1 0.75 0.50 p v m a a htssop32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad sot549- 1 a max. 1.1 0 2.5 5 mm scale pin 1 index mo-153
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 47 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 48 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 2 and 13 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 21 . table 12. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 13. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 49 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 21. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 50 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 14. revision history table 14. revision history document id release date data sheet status change notice supersedes uja1075a v.1 20100709 product data sheet - -
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 51 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
uja1075a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 9 july 2010 52 of 53 nxp semiconductors uja1075a high-speed can/lin core system basis chip export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors uja1075a high-speed can/lin core system basis chip ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 9 july 2010 document identifier: uja1075a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 can transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 control and diagnostic features . . . . . . . . . . . . 3 2.6 voltage regulators. . . . . . . . . . . . . . . . . . . . . . . 3 3 ordering information . . . . . . . . . . . . . . . . . . . . . 4 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 system controller . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.2 off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.3 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.4 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.5 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1.6 overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2.3 wd_and_status register. . . . . . . . . . . . . . . . . 12 6.2.4 mode_control register . . . . . . . . . . . . . . . . . . 13 6.2.5 int_control register . . . . . . . . . . . . . . . . . . . . . 14 6.2.6 int_status register. . . . . . . . . . . . . . . . . . . . . . 16 6.3 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 16 6.4 watchdog (uja1075a/xx/wd versions) . . . . . 17 6.4.1 watchdog window behavior . . . . . . . . . . . . . . 17 6.4.2 watchdog timeout behavior . . . . . . . . . . . . . . 17 6.4.3 watchdog off behavior . . . . . . . . . . . . . . . . . . 18 6.5 system reset. . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.1 rstn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.2 en output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.3 limp output . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 power supplies . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.1 battery pin (bat) . . . . . . . . . . . . . . . . . . . . . . 20 6.6.2 voltage regulator v1 . . . . . . . . . . . . . . . . . . . . 20 6.6.3 voltage regulator v2 . . . . . . . . . . . . . . . . . . . . 22 6.7 can transceiver . . . . . . . . . . . . . . . . . . . . . . . 22 6.7.1 can operating modes . . . . . . . . . . . . . . . . . . 22 6.7.1.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7.1.2 lowpower/off modes . . . . . . . . . . . . . . . . . . . 23 6.7.2 split circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.7.3 fail-safe features . . . . . . . . . . . . . . . . . . . . . . 24 6.7.3.1 txdc dominant time-out function . . . . . . . . . 24 6.7.3.2 pull-up on txdc pin . . . . . . . . . . . . . . . . . . . 24 6.8 lin transceiver. . . . . . . . . . . . . . . . . . . . . . . . 24 6.8.1 lin operating modes . . . . . . . . . . . . . . . . . . . 25 6.8.1.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.8.1.2 lowpower/off modes . . . . . . . . . . . . . . . . . . . 25 6.8.2 fail-safe features . . . . . . . . . . . . . . . . . . . . . . 25 6.8.2.1 general fail-safe features. . . . . . . . . . . . . . . . 25 6.8.2.2 txdl dominant time-out function . . . . . . . . . 25 6.9 local wake-up input . . . . . . . . . . . . . . . . . . . . 26 6.10 interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 27 6.11 temperature protection . . . . . . . . . . . . . . . . . 27 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28 8 thermal characteristics . . . . . . . . . . . . . . . . . 30 9 static characteristics . . . . . . . . . . . . . . . . . . . 32 10 dynamic characteristics. . . . . . . . . . . . . . . . . 40 11 test information . . . . . . . . . . . . . . . . . . . . . . . 45 11.1 quality information . . . . . . . . . . . . . . . . . . . . . 45 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 46 13 soldering of smd packages . . . . . . . . . . . . . . 47 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 47 13.2 wave and reflow soldering. . . . . . . . . . . . . . . 47 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 50 15 legal information . . . . . . . . . . . . . . . . . . . . . . 51 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 16 contact information . . . . . . . . . . . . . . . . . . . . 52 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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